1. Field of the Invention
The present invention relates to semiconductor packaging substrates, and, more particularly, to a packaging substrate for carrying semiconductor chip, a method of fabricating the packaging substrate, a package structure having the packaging substrate, and a method of fabricating the package structure.
2. Description of Related Art
With the rapid development of electronics industry, electronic products gradually trend towards multi-function and high-performance. In order to meet the requirements of the miniaturization of semiconductor package units, it is developed towards the reduction of the thickness of a packaging substrate carrying chips. The packaging substrate currently for carrying the chips can be classified into hard material substrates and soft material substrates. The packaging substrate for a ball grid array (BGA) package is usually subjected to a hard material substrate.
Referring to FIGS. 1A-1D, cross-sectional diagrams illustrating a method of fabricating a packaging substrate 1a having two layers of circuits in accordance with the prior art are provided.
As illustrated in FIG. 1A, a core layer 13 having a first surface 13a and a second surface 13b opposite to the first surface 13a is provided. Copper layers 11a and 11b are disposed on the first surface 13a and the second surface 13b, respectively.
As illustrated in FIG. 1B, a plurality of through holes 130 are formed in the core layer 13 from the second surface 13b of the core layer 13 via a laser drilling technique such that the copper layer 11a on the first surface 13a is exposed from the through holes 130.
As illustrated in FIG. 1C, the copper layers 11a and 11b are patterned. First and second circuit layers 12 and 14 are respectively formed on the first and second surfaces 13a and 13b by electroplating through a conductive seed-layer 10. Conductive vias 140 are formed in the through holes 130 and electrically connect the first and second circuit layers 12 and 14. The first and second circuit layers 12 and 14 have a plurality of first and second conductive pads 120 and 141, respectively.
As illustrated in FIG. 1D, insulating protection layers 15 are formed on the first and second surfaces 13a and 13b, respectively, and the conductive vias 140 are filled with a portion of the insulating protection layer 15. A plurality of openings 150 are foamed in the insulating protection layers 15, and the first and second conductive pads 120 and 141 are exposed from the openings 150, and the packaging substrate 1a is thus formed. Surface treatment layers 15a are formed on the exposed surfaces of the first and second conductive pads 120 and 141.
As illustrated in FIG. 1E, a chip 170 is disposed on one of the insulating protection layers 15 and electrically connected to the second conductive pads 141 via conducting wires 17. An encapsulant 18 is formed to cover the chip 170. Solder balls 19 are disposed on the first conductive pads 120, and a package structure 1 is thus obtained. In order to satisfy the requirements of miniaturization and reliability, the thickness of the core layer 13 can be reduced to 60 μm.
However, with the increasing demand for miniaturization, the core layer 13 having a thickness of 60 μm cannot satisfy the increasing requirement for miniaturization of package units. If the thickness of the core layer 13 is less than 60 μm, the total thickness R of the packaging substrate 1a will be less than 130 μm and thus leads to poor production operability. For example, the packaging substrate 1a easily sticks during moving between process work stations, and thus is adverse for production. Even if production is performed, during transportation or packaging, it is easily bended or broke due to reduced thickness, and thus leads to useless or defected products.
Further, in order to facilitate production of fine pitch circuits, the thickness of the copper layers 11a and 11b is close to 3 μm, so that the copper layer 11a is easily penetrated by laser. In order to prevent the laser from penetrating the copper layer 11a, laser energy is typically adjusted less so as to increase the number of laser shots. As a result, this leads to prolonged process time and increased costs.
Also, in a fabricating method of the packaging substrate 1a in accordance with the prior art, since the depth of the through hole 130 is too deep, electroplating performance is poor to prevent voids from occurrence during the formation of the conductive vias 140, and it also easily has voids while the insulating protection layer 15 is applied to fill the conductive vias 140.
Therefore, how to overcome the problems of the prior art as described above, is becoming the topic in urgent need to be solved.